// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:07 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  pcs_raw_gen_rst_sync.v
//
//  Capture asynchronous reset pulse and synchronize into local clock domain.
//
//  Original Author: Chris Jones
//  Current Owner:   Dom Spagnuolo
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: yilin $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_gen_rst_sync.v $
//    $DateTime: 2016/03/09 11:36:56 $
//    $Revision: #1 $
//
////////////////////////////////////////////////////////////////////////////// 

module dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync
 #(parameter ATPG_COV = 1)
 (
  output wire sync_rst,
  input  wire clk,
  input  wire scan_mode_i,
  input  wire scan_set_rst_i,
  input  wire async_rst
);

// %%SYNTH:
//   set_false_path -from $nonscan_clks -to $inst/d_s1_reg/preset
//   set_false_path -from $nonscan_clks -through $inst/d_s1_reg/preset
//   set_false_path -from $scan_clks -through $inst/d_s1_reg/preset -to $nonscan_clks
//   set_false_path -from $nonscan_clks -to $inst/d_s2_reg/preset
//   set_false_path -from $nonscan_clks -through $inst/d_s2_reg/preset
//   set_false_path -from $scan_clks -through $inst/d_s2_reg/preset -to $nonscan_clks
//   set_false_path -from $nonscan_clks -to $inst/d_s3_reg/preset
//   set_false_path -from $nonscan_clks -through $inst/d_s3_reg/preset
//   set_false_path -from $scan_clks -through $inst/d_s3_reg/preset -to $nonscan_clks
//
// ASSERT: somehow prove that async_rst can never glitch.  This should
//         be done formally... simulation may not catch it
//

// MUX in the reset for ATPG
//
wire async_scan_rst;
dwc_e12mp_phy_x4_ns_gen_mux scan_async_rst_mux (
  .out (async_scan_rst),
  .sel (scan_mode_i),
  .d0  (async_rst),
  .d1  (scan_set_rst_i)
);

reg d_s1, d_s2, d_s3;
always @(posedge clk or posedge async_scan_rst) begin
  if (async_scan_rst) begin
    d_s1 <= 1'b1;
    d_s2 <= 1'b1;
    d_s3 <= 1'b1;
  end 
  else begin
    d_s1 <= 1'b0;
    d_s2 <= d_s1;
    d_s3 <= d_s2;
  end
end

dwc_e12mp_phy_x4_ns_gen_mux scan_sync_rst_mux (
  .out (sync_rst),
  .sel (scan_mode_i),
  .d0  (d_s3),
  .d1  (scan_set_rst_i)
);

generate if (ATPG_COV == 1) begin: gen_atpg_cov
  // Test cover point for async_rst
  reg atpg_cov;
  always @(posedge clk or posedge scan_set_rst_i) begin
    if (scan_set_rst_i)
      atpg_cov <= 1'b0;
    else
      atpg_cov <= async_rst;
  end
end
endgenerate
    
endmodule
